1 * this specification are subject to be changed without notice. EM23C3220 series 4m x 8/2m x 16 cmos rom 10.22.1997 preliminary preliminary preliminary preliminary preliminary EM23C3220 series 4m x 8/2m x 16 cmos rom general description the EM23C3220 series is a 5v only, 32m-bit, read only memory. it is organized as 4m x 8 bits (byte mode) or as 2m x 16 bit (word mode) depending on byte (pin 33/44sop) voltage level. EM23C3220 has a static standby mode, and has an access time of 100/120/150/200ns. it is designed to be compatible with all microprocessors and similar applications in which high performance, large bit storage and simple interfacing are important design considerations. EM23C3220 offers automatic power-down, with power down controlled by the chip (ce/ce) input. when ce/ ce is not selected, the device automatically powers down and remains in a low-power standby mode as long as ce/ce stays in the unselected mode. the oe/oe inputs as well as ce/ce input may be programmed either active high or low. features ? switchable configuration. ? 4m x 8 (byte mode) 2m x 16 (word mode) ? single +5v power supply. ? fast access time : 100/120/150/200 ns (max). ? totally static operation. ? completely ttl compatible. ? operating current : 60 ma. ? standby current : 100 m a ? package: EM23C3220ep, - 42 pins 600 mil dip EM23C3220em , - 44 pins 500 mil sop. pin assignments a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce/ce vss oe/oe d0 d8 d1 d9 d2 d10 d3 d11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 a20 vss d15/a-1 d7 d14 d6 d13 d5 d12 d4 vcc EM23C3220ep nc a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce/ce vss oe/oe d0 d8 d1 d9 d2 d10 d3 d11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a20 a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 byte vss d15/a-1 d7 d14 d6 d13 d5 d12 d4 vcc EM23C3220em pdip sop
* this specification are subject to be changed without notice. 2 10.22.1997 EM23C3220 series 4m x 8/2m x 16 cmos rom preliminary preliminary preliminary preliminary preliminary block diagram a0~a20 address input d0~d14 data output ce/ce chip enable input oe/oe output enable input byte word/byte selection d15/a-1 d15 (word mode)/ lsb addr. (byte mode) v cc power supply pin (+5v) v ss ground pin symbol function pin descriptions function descriptions byte mode (byte =v ss ) mode ce oe/oe d15/a-1 d0-d7 supply current note non selected h x x high z standby (i cc2 )1 selected/non output l l/h x high z operating (i cc1 )1 selected l h/l a-1 input dout operating (i cc1 )1 word mode (byte =v cc ) mode ce oe/oe d15/a-1 d0-d14 supply current note non selected h x high z high z standby (i cc2 )1 selected/non output l l/h high z high z operating (i cc1 )1 selected l h/l dout dout operating (i cc1 )1 note1 : x=h or l x-decoder y-decoder control logic . . . . . . . 32m bit rom array y-select output buffers . . . . . . . ce/ce oe/oe byte d15/a-1 vcc vss a0~a20 address inputs d0~d14
3 * this specification are subject to be changed without notice. EM23C3220 series 4m x 8/2m x 16 cmos rom 10.22.1997 preliminary preliminary preliminary preliminary preliminary absolute maximum ratings items sym. condition rating operating temperature t opr 0 to 70 c storage temperature t str -65 c to 125 c input voltage v in - 0.5v to 7.0v output voltage v out - 0.5v to 7.0v supply voltage v cc - 0.5v to 7.0v power dissipation 1.0w capacitance t a =25 c, f=1.0 mhz (note 2) parameter sym. condition min. max. unit input capacitance c in v in =0v 10 pf output capacitance c out v out =0v 10 pf dc electrical characteristics (v cc = 5v 10%, t a =0~70 c) parameter sym. condition min. max. unit note output high voltage v oh i oh = -1.0ma 2.4 v output low voltage v ol i ol = 2.1ma 0.4 v input high voltage v ih 2.2 v cc +0.3 v input low voltage v il -0.3 0.8 v input leakage current i li v in = 0v to 5.5v 10 m a output leakage current i lo v out =0v to 5.5v 10 m a power-down supply current i cc3 ce > v cc -0.2v 100 m a standby supply current i cc2 ce = v ih 2 ma operating supply current i cc1 60 ma 1 * notice : stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not imlied. exposure to absoute maximum rating conditions for extended period may affect reliability.
* this specification are subject to be changed without notice. 4 10.22.1997 EM23C3220 series 4m x 8/2m x 16 cmos rom preliminary preliminary preliminary preliminary preliminary ac electrical characteristics (v cc = 5v 10%, t a =0~70 c) 3220-10 3220-12 3220-15 3220-20 parameter sym. min. max. min. max. min. max. min. max. unit condition cycle time t cyc 100 120 150 200 ns address access time t acc 100 120 150 200 ns output hold time after address change t oh 10 10 10 10 ns chip enable access time t ace 100 120 150 200 ns output enable/chip select access time t aoe 60 70 80 90 ns output low z delay t lz 0 0 0 0 ns note 3 output high z delay t lh 70 70 70 70 ns note 4 byte access time t bha 100 120 150 200 ns byte output hold time t ohb 00 0 ns byte output delay time t bhz 70 70 70 70 ns byte output set time t blz 10 10 10 10 ns note: 1. measured with device selected at f=5 mhz and output unloaded. 2. this parameter is periodcally sampled and is not 100% tested. 3. output low-impedance delay (tlz) is measured from ce going low. 4. output high-impedance delay (thz) is measured from ce going high. ac test conditions input pulse levels 0.4v to 2.4v input rise and fall time 10 ns input timing level 1.5 v output timing level 0.8v and 2.0v output load see figure 1 775 dout 100pf* 1250 +5v * including scope and jig. fig.1 output load circuit
5 * this specification are subject to be changed without notice. EM23C3220 series 4m x 8/2m x 16 cmos rom 10.22.1997 preliminary preliminary preliminary preliminary preliminary timing diagram valid address valid data t aa t oh address data inputs out t cyc t data out oe ce t lz t ace t aoe hz high-z high-z t aa t oh valid data t ohb t bhz t blz t bha valid data valid data a-1 byte d0-d7 d15-d8 propagation delay from address (ce/oe=active) propagation delay from chip enable (address valid) propagation delay from chip enable (address vaild)
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